1. Technical Field
This invention generally relates to semiconductor devices, and more specifically relates to power conservation in semiconductor devices.
2. Background Art
The proliferation of electronics in our modern world is in large part due to integrated circuit semiconductor devices. Integrated semiconductor devices are designed and used in almost every electronic device today. In many applications power consumption is a critical issue for several reasons. For example, in portable devices such as wireless telephones, battery life and battery size is a primary design concern. Consumers want the portable electronic device to run as long as possible using a single battery charge and also want the device, including the battery to be as small and portable as possible. Thus, it is strongly desirable to be able to decrease power consumption of the device such that battery life can be extended and/or the size of the battery decreased.
In other applications power consumption is critical because it is directly related to the amount of heat generated by a device. A semiconductor device that consumes more power will generate more heat. In applications where heat sensitivity is a critical factor, reducing the power consumption reduces the heat generated by the device.
One factor that leads to excessive power consumption is unnecessary node toggling. In CMOS circuits, the power consumed is directly proportional to the size of the capacitive load being switched, and to the frequency with which it is being switched. In a typical random logic network, a given logic circuit output might switch many times in a single clock cycle before settling down on its final value. This phenomenon is due to the fact that in a multi-input circuit, input signals can arrive at different times due to different path delays and load conditions. Each time an input signal arrives, it can cause a switch on the output, causing unnecessary multiple switches each cycle that increase active power yet have no redemptive value since they have no effect on the final logic state.
Turning now to FIGS. 9-10, an exemplary logic gate 900 is illustrated in FIG. 9, and a timing chart 910 for the logic gate 900 is illustrated in FIG. 10. The logic gate 900 comprises an AND-OR-INVERTOR logic gate, but the problem is equally applicable to any type of logic circuit. The timing chart 910 illustrates how the unnecessary toggling can occur as a result of different inputs arriving at different times during a clock cycle. At the beginning of the clock cycle, at time T.sub.1, the logic circuit starts out with a low output. Partially into the clock cycle, at time T.sub.2, the input B change arrives. This change is propagated through the logic gate 900, and causes the output of the logic gate to toggle. At time T.sub.3, input A change arrives, causing the output to toggle a second time. Finally, at time T.sub.4, the input C changes, resulting in a third and final toggle. Thus, the output of the logic gate experienced two unnecessary toggles at times T.sub.2 and T.sub.3 before finally stabilizing at the final output at time T.sub.4. These unnecessary toggles, generally called glitches, consume power as they charge and discharge any capacitance connected to the out, without producing useful work.
Therefore, there exists a need to provide reduced power consumption by reducing unnecessary node toggling in semiconductor devices.